16 Byte Tx/Rx FIFOs, Data Rate up to 5.3Mbps, H/W Flow Control (Auto-RTS and Auto-CTS)

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SB16C554A is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter). Each channel can be set as FIFO mode, reducing CPU overhead for I/O. Each channel performs serial-to-parallel conversion of the data received from the peripheral devices to CPU, or vice versa. The CPU can read all status of the UART at any time during the functional operation. The status information includes the type and condition of the transfer operations being performed by the UART as well as any error conditions such as parity, overrun, framing and break interrupt. With the complete modem-control capability and the interrupt system that can be programmed to the user’s requirement, SB16C554A minimizes the computing required to handle the communication links.

Advanced Features

SB16C554A has more advanced features which can be applied to various circuits. Each function may make development much easier, and make circuit design simple but powerful. Several functions below are only a portion of powerful Quad-UART, SB16C554A. For more descriptions, refer to SB16C554A Data Sheet.

16-byte FIFO

SB16C554A ha0s 16-byte TX/RX FIFO to reduce CPU overhead for I/O. In this case, the internal FIFOs are enabled and 16 bytes plus 3 bit of error data per byte can be stored in both receiver side of the FIFO and transmitter side of the FIFO. The following features can be enabled: the FCR (FIFO Control Register), Write-only Register, sets the trigger level for FIFO to transmit, and selects the type of DMA signalling.

Programmable Baud Rate Generator

SB16C554A has a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to 2^16-1 (or 65535), and producing a x16 clock for driving the internal transmitter logic. Provisions are also included to use this clock to drive the receiver logic. Customized baud rate can be achieved by selecting the proper divisor in the baud rate generator.

Fully Prioritized Interrupt System Control

In order to provide the minimum overhead for I/O during data transfer, SB16C554A prioritizes interrupts of ‘Receiver Line Status’, ‘Received Data Ready’, ‘Transmitter Holding Register Empty’, and ‘Modem Status’ into 4 levels and records these in the Interrupt Identification Register. When the CPU accesses the IIR (Interrupt Identification Register), SB16C554A freezes all interrupts and indicates the highest priority pending to the CPU.

Fully Programmable Serial Interface Characteristics

When designing circuits, users can program all the serial interface characteristics; 5, 6, 7, and 8-bit characters. When a parallel data is converted to serial, its character bit may be selected by users. The users or developers can determine and program the width of characters from 5 to 8 bit at their convenience. Even, odd or no parity bit are not required to convert serial data. Even, odd or no parity bit are not necessary and can be programmed. That is same for 1, 1.5, 2 stop-bit. It will convert serial data to 1, 1.5, 2 stop-bit and can be programmed.

False Start Bit Detection

SB16C554A can detect the false start bit when receiving the data. When the serial data arrives, the start bit is asserted to low and SB16C554A recognizes it. And in the middle of the clock, SB16C554A checks the start bit whether it keeps asserted-low. If it keeps low, SB16C554A allows it as a right start-bit and if it goes back high, SB16C554A regards it as a false start bit.

Generates or Detects Line Break

SB16C554 has a LCR (Line Control Register) which can generate the break signal 0 (zero) on TxD output. Users can use it when they want to force the TxD output to 0. SB16C554 can also detect the Line Break. After the start bit arrives, data and stop bits keeps being 0 to the end, SB16C554A recognizes it as a Line Break.

Internal Diagnostic Capabilities

SB16C554A provides a local loop back feature for diagnosis of the channel. A bit in MCR (Modem Control Register) enables this mode. In the Diagnostic mode, the transmitted data are immediately received. This allows the processor to verify the path of transmitted or received data of the selected serial channel.

Art.-ID 101367
Zustand Neu
Hersteller SystemBase
Herstellungsland Demokratische Volksrepublik Korea
Inhalt 1 Stück


  Features Integrated Four Improved SB16C550A UART
In the FIFO mode, Each channel’s transmitter and receiver is buffered
  with 16 Byte FIFO to reduce the number of interrupts to CPU.
Adds or deletes standard asynchronous communication
  bits(start, stop, parity) to or from the serial data.
Holding Register and Shift Register eliminate needs for the precise
  synchronization between the CPU and serial data.
Independently controlled transmit, receive, line status and data interrupts.
Programmable Baud Rate Generators which allow division of any input
  reference clock by 1 to 216-1 and generated an internal 16x clock.
Modem control functions (RTS#, CTS#, DTR#, DSR#, DCD# and RI#)
Independent receiver clock input.
Fully programmable serial interface characteristics.
   – 5, 6, 7 or 8 bit characters.
   – Even, Odd, No parity bit
   – 1, 1.5, 2 Stop bit generation.
   – Like other general UARTs, SB16C554A checks one stop bit, no matter how many they are.
False start bit detection and Generates or Detects Line Break.
Internal diagnostic capabilities : Loopback controls for communication link Fault isolation.
Fully prioritized interrupt system controls.
Programmable Auto-RTS# and Auto-CTS#
CTS# Controls Transmitter in Auto-CTS# Mode
RCV FIFO Contents and Threshold Control RTS# in Auto-RTS# Mode
3.3V Operation
80-pin TQFP, 68-pin PLCC, 64-pin LQFP, 68-pin QFN Packages
  Application Multi-port RS-232/RS-422/RS-485 Cards
Remote Access Servers
Factory Automation and Process Control
Ethernet Network to Serial Ports
Network Management
Point-of-Sale Systems