Connects Local Legacy Bus and PCI Bus, Supports 32 bit Bus (33MHz or 66MHz), Supports ISA like Local Legacy Bus (transaction speed up to 66MHz)
For years, the PCI Local Bus has been the most powerful and widely used standard bus in general PCs, industrial computers, various servers and workstations. This tendency will continue for the time being for its convenience and high efficiency. But in spite of this convenience and compatibility, the development process of PCI is quite difficult and therefore has been a burden to developers.
However, from now on, the developers do not need to worry about developing a PCI target device. SB4002A is a kind of bridge which connects Local Legacy Bus and PCI Bus. It is extremely useful in converting an ISA bus device or an old style device to a PCI target device. SB4002A provides the best solution for you to upgrade an existing 33MHz PCI target device to a 66MHz PCI target device. SB4002A is the only PCI Target Interface Controller that supports 66MHz operating frequency, and guarantees the best performance.
SB4002A has many advanced features which can be applied to various fields. Each function facilitates easier development, and simple but powerful circuit design. The functions specified below are only a portion of the powerful functions of SB4002A. Please refer to the SB4002A data sheet for further information.
33/66MHz Target Interface Chip
Conventional PCI target interface chips have only 33MHz operating frequency. But SB4002A supports up to 66MHz, so the users who want to upgrade 33MHz device to 66MHz can use this chip. Despite its high frequency, it shows stable performance and supports burst transfer up to 264MBytes/sec. It is the fastest speed in comparison with other chips.
Basically, PCI bus is based on little endian. Because the device connected to the Legacy bus can support little endian itself, SB4002A supports conversion between the little endian data and the big endian data.
5 Base Address Registers
SB4002A offers 5 base address registers for memories and I/O. Each spaces has CS (Chip Select) and 5 interrupt lines. Developers can use these spaces as however they want. The figure below shows an example of using SB4002A with a UART, memories, and I/O as a PCI target adapter card.
Real Access / Delayed Access
SB4002A supports Real/Delayed Access. Real Access provides the real time data transfer by executing the PCI transaction and the legacy bus transaction at the same time. Delayed Access transmits data through the transaction on the legacy bus after the device completes the transaction on the PCI bus.
PCI Power Management Interface
SB4002A supports PCI Power Management Interface Specification Revision 1.1. It provides the power management-related signal to control the power supply of the PCI.
CompactPCI and CompactPCI Hot Swap
CompactPCI is the specification made by applying the existing specification of PCI local bus for general PC to an industrial PC. The algorithms such as bus protocol are same as those of the existing PCI, except for the electrical features and the mechanical features. Hot Swap is one of the functions that reinforces the industrial aspect of CompactPCI. The function enables you to delete or insert the CompactPCI board while the power is connected to the system. SB4002A follows the CompactPCI Hot Swap Specification 1.0.
Vital Product Data (VPD)
VPD is a capability register prepared to provide additional information on the system and the device. It is located in the memory devices such as serial EEPROM. The data are accessed through the VPD capable register in the Configuration Space Header. SB4002A adopts the VPD format defined in PCI Specification Revision 2.3.
General Purpose I/O Interface
SB4002A provides 8 GPIO ports. In order to control the 8 GPIO ports, SB4002A also provides GPIO Output Enable Register, GPIO Output Register and GPIO Input Register.
|Herstellungsland||Demokratische Volksrepublik Korea|
|Features||PCI Local Bus Spec Rev 2.3 compliant|
|PCI Burst Transfers up to 264Mbytes/sec|
|(32bit Bus @ 33/66MHz)|
|Supports the ISA like Local Legacy Bus|
|(transaction speed up to 66MHz)|
|Selectable data width (8/16/32 bits) and little/big endian at the legacy bus|
|PCI Power Management v1.1|
|Supports CompactPCI and CompactPCI Hot Swap|
|Supports 5 PCI to Local Address Spaces|
|(Memory or I/O selection is possible)|
|Provides Chip Select and Interrupt lines at each 5 addresses|
|Capable of controlling the Read/Write timing|
|Supports the Delayed Read/Write by using a FIFO|
|Downloads the Configuration header data from the external Serial ROM|
|176 pin TQFP Package|
|Electrically compatible I/O pins with PCI Local Bus|
|Specification v3.0(+3.3V I/O, Input 5V tolerance)|
|Application||Various PCI Target Adapter Card|
|Digital IO and Analog IO Card|
|Data Control Card|
|Serial MultiPort and Serial Mode Card|